This invention relates generally to automatic test equipment for integrated circuits, and in particular to methods and circuits for precisely placing signal transitions for use in testing integrated circuits.
Most semiconductor devices are tested at least once using some form of automated test equipment (generally, a xe2x80x9ctesterxe2x80x9d). Modern semiconductor chips have many pins and, to fully test the semiconductor device, the tester must generate and measure signals for all of these pins simultaneously.
Testers generally have a xe2x80x9cper-pinxe2x80x9d architecture in which separate xe2x80x9cchannelsxe2x80x9d within the tester generate or measure one signal corresponding to a single input or output pin on a device under test. Each channel is separately controlled to generate or measure a different signal. A pattern generator, the function of which is to send commands to each channel to generate or measure one test signal for each of many test periods, controls the various channels. Each channel generally contains at least one edge generator programmed to generate a signal transition, or xe2x80x9cedge,xe2x80x9d at a certain time relative to the start of each test period.
Testers must place accurately timed edges at the various pins of a device under test to make accurate pin-to-pin measurements. When properly calibrated, testers with hundreds or even thousands of channels are only able to reduce the relative error between channels to somewhere in the range of xc2x1150 ps to xc2x11 ns. All measurements require at least two edges be placed, so the cumulative measurement error inherent in the tester can contribute somewhere between 300 ps and 2 ns of uncertainty. Unfortunately, this inherent tester error often exceeds the value of the parameter being measured. There is therefore a need for a means of more precisely placing edges on the pins of devices under test.
The present invention provides an accurate means of placing signal transitions, or xe2x80x9cedges,xe2x80x9d simultaneously on two or more pins of an integrated circuit (IC). The inventive circuit is particularly useful for testing programmable logic devices, which can be programmed to include one or more coincidence detectors with which to place edges relative to one another on different pins.
In accordance with an embodiment of the invention, a conventional tester is connected to an integrated circuit, such as a programmable logic device. The integrated circuit is adapted to include a coincidence detector that compares the timing of edges on two input pins of the integrated circuit. The coincidence detector indicates when the two edges are coincident, allowing an operator of the tester to adjust the tester to achieve coincidence. The amount of offset necessary to provide coincident edges is then stored in a database for later use in deskewing edges for test.
In some embodiments, the integrated circuit is provided with a number of coincidence detectors that collectively determine the timing offsets necessary to adjust the tester to create coincident signals on every input pin of the integrated circuit.
In those embodiments in which the integrated circuit is a programmable logic device, the resources used to instantiate the one or more coincidence detectors can be used to instantiate other components once the test configuration is calibrated.